1. Field of the Invention
The present invention relates to a semiconductor memory device and method for manufacturing the same, and more particularly, to a dynamic random access memory (DRAM) having a stack-shaped capacitor and a method for manufacturing the same.
2. Description of the Related Art
A dynamic random access memory (DRAM) among semiconductor memory devices is comprised of one transistor and one capacitor. Thus, in order to serve as a memory device, the DRAM must have sufficient capacitance. There is no problem when the design rule of the memory device is wide. However, as the memory device becomes highly integrated, its design rule becomes extremely dense and an area for each memory device becomes narrower, and thus, area per cell also decreases. A stack-shaped capacitor has been developed to obtain sufficient capacitance as the area becomes narrower. The stack-shaped capacitor can increase a surface area by forming an electrode with high depth even though the occupied area of the capacitor decreases. Thus the required capacitance of the capacitor can be obtained even though the design rule of the memory device becomes finer. However, in the stack-shaped capacitor, when the stack-shaped capacitor forms a storage node, a step between the cell area and a peripheral area becomes very severe. As a result, a metal interconnection process cannot be performed well due to an extreme pattern-thinning phenomenon caused by diffraction and irregular reflection of light, which is exposed due to a high step between a cell area and the peripheral area during a subsequent photolithographic process for metal interconnections in a case where a predetermined planarization process is not performed.
Thus, in a conventional planarization process between the cell area and the peripheral area, a very thick interlayer dielectric (ILD) film is formed on the surface of a semiconductor substrate after a capacitor process is completed. The cell area having a high step is opened after a predetermined photolithographic process, and then, the ILD film in the cell area is etched to a predetermined thickness through dry etching, and thereby removed. Then, the step between the cell area and the peripheral area is slightly decreased. The thick ILD film is again formed on the surface of the semiconductor substrate and is polished and removed and thereby planarized to enable the metal interconnection process on the entire surface of the semiconductor substrate through chemical mechanical polishing (CMP).
However, the photolithographic process for opening the cell area and a dry etching process is added to the conventional planarization process between the cell area and the peripheral area, and an additional planarization process using CMP is accompanied by a subsequent process, thus increasing the number of processes. Moreover, the photolithographic process and the CMP process are included, and thus the reliability of production is reduced, and the period of a manufacturing process becomes longer, and costs increase.